In a system of multiple coupled digital phase-locked loops (DPLLs), a receiving DPLL can add to a frequency offset from a loop filter within the receiving DPLL using a frequency offset received from one or multiple sourcing DPLLs. If one of the sourcing DPLLs switches to another input reference clock with a different fractional frequency offset (ffo), or the receiving DPLL switches from one sourcing DPLL to another sourcing DPLL, the added frequency offset could incur a rapid change. The rapid change could cause a large phase transient on the output of the receiving DPLL. A mechanism is needed to prevent re-arrangements in the sourcing of the DPLL coupling or input reference switches from causing a phase transient on the output of the receiving DPLL.
It would be desirable to implement hitless re-arrangements in coupled DPLLs.